[SiByte] RE: weird sb1250 behavior

[Ralf Baechle]

On Fri, May 28, 2004 at 01:11:38PM -0700, Adam Kiepul wrote:

> There is a possible cache line read-after-write pseudo-dependency that, along with the code alignment in terms of the instruction pair doublewords, may do something weird to the sb1250 pipeline. Just my guess.

memcpy's source deals with what probably is another instance of the same
effect:

#ifdef CONFIG_CPU_SB1
        nop                             # improves slotting
#endif

  Ralf